A floating-gate MOS learning array with locally computed weight updates

A Floating-Gate MOS Learning Array with Locally Computed Weight Updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weights are stored as floating-gate charge; they are nonvolatile, but can increase when we apply a row-...

Floating-gate Mos Synapse Transistors

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation...

Dynamic Charge Restoration of Floating Gate Subthreshold MOS Translinear Circuits

We extend a class of analog CMOS circuits that can be used to perform many analog computational tasks. The circuits utilize MOSFET’s in their subthreshold region as well as capacitors and switches to produce the computations. We show a few basic currentmode building blocks that perform squaring, square root, and multiplication/division which should be sufficient to gain understanding of how to ...

C Hapter 3 Quasi Floating - Gate Mos Transistor